View CDK3404_4693516.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
CDK3404
8-bit, 180MSPS, Triple Video DACs
CDK3404 8-bit, 180MSPS, Triple Video DACs
FEATURES
n n n n n n n n
General Description
CDK3404 is a low-cost triple D/A converters that are tailored to fit graphics and video applications where speed is critical. CMOS-level inputs are converted to analog current outputs that can drive 25-37.5 loads corresponding to doubly-terminated 50-75 loads. A sync current following SYNC input timing is added to the IOG output. BLANK will override RGB inputs, setting IOG, IOB and IOR currents to zero when BLANK = L. Although appropriate for many applications, the internal 1.25V reference voltage can be overridden by the VREF input. Few external components are required, just the current reference resistor, current output load resistors, bypass capacitors, and decoupling capacitors. Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is guaranteed from -40C to +125C.
8-bit resolution, 180MSPS 2.5% gain matching 0.5% linearity error Sync and blank controls 1.0Vpp video into 37.5 or 75 load Internal bandgap voltage reference Low glitch energy Single +3.3V power supply
APPLICATIONS
n
Video signal conversion - RGB - YCBCR - Composite, Y, C Multimedia systems Image processing PC Graphics
n n n
Block Diagram
SYNC BLANK SYNC
Rev 3A
G7-0
8
8-bit D/A Converter
IO G
B7-0
8
8-bit D/A Converter
IO B
R7-0 CLOCK
8
8-bit D/A Converter
IO R COMP R REF V REF
+1.25V Ref
Ordering Information
Part Number CDK3404CTQ48 CDK3404CTQ48Y Package TQFP-48 TQFP-48 Pb-Free Yes Yes RoHS Compliant Yes Yes Operating Temp Range -40C to +125C -40C to +125C Packaging Method Package Quantity Tray Tray 250 1,250
Moisture sensitivity level for all parts is MSL-3.
(c)2009 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
Pin Configuration TQFP-48
GND R7 R6 R5 R4 R3 R2 R1 R0 GND GND NC
CDK3404 8-bit, 180MSPS, Triple Video DACs
48 47 46 45 44 43 42 41 40 39 38 37 GND G0 G1 G2 G3 G4 G5 G6 G7 BLANK SYNC VDDD 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25
TQFP CDK3404
RREF VREF COMP IOR IOG VDDA VDDA IOB GND GND CLOCK NC
Pin Assignments
Pin No. 26 47-40 9-2 23-16 Controls 11 10 Video Outputs 33 32 29 35 36 34 30, 31 12 1, 14, 15, 27, 28, 38, 39, 48 13, 24, 25, 37 IOR IOG IOB VREF RREF COMP VDDA VDDD GND Red Current Output Green Current Output Blue Current Output Voltage Reference Output/Input Current-Setting Resistor Compensation Capacitor Analog Power Supply Digital Power Supply Ground SYNC BLANK Sync Pulse Input Blanking Input Pin Name CLK R7-0 G7-0 B7-0 Description Clock Input Red Pixel Data Inputs Green Pixel Data Inputs Blue Pixel Data Inputs Clock and Pixel I/O
NC GND GND B0 B1 B2 B3 B4 B5 B6 B7 NC
13 14 15 16 17 18 19 20 21 22 23 24
Rev 3A
Voltage Reference
Power and Ground
NC
No Connect
(c)2009 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
CDK3404 8-bit, 180MSPS, Triple Video DACs
Parameter Power Supply Voltage VDDA (Measured to GND) VDDD (Measured to GND) Digital Inputs Applied Voltage (measured to GND)(2) Forced Current(3,4) Analog Inputs Applied Voltage (measured to GND)(2) Forced Current Analog Outputs Applied Voltage (measured to GND)(2) Forced Current(3,4) Short Circuit Duration (single output in HIGH state to GND)
(3,4)
Min -0.5 -0.5 -0.5 -5.0 -0.5 -10.0 -0.5 -60.0
Max 4.0 4.0 VDDD + 0.5 5.0 VDDA + 0.5 10.0 VDD + 0.5 60.0 unlimited
Unit V V V mA V mA V mA sec
Reliability Information
Parameter Temperature Operating, Ambient Junction Lead Soldering (10 seconds) Vapor Phase Soldering (1 minute) Storage Package Thermal Resistance (JA)
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
3 2.5 2
TQFP-48
Min -40
Max 125 150 300 220 150 65
Unit C C C C C C/W
Rev 3A
-65
CDK3404 Power Derating
Maximum Power Dissipation (W)
1.5 1 0.5 0 -40
-20
0
20
40
60
80 100 120
Ambient Temperature (C)
Recommended Operating Conditions
Symbol
VDD VREF CC RL TA
Parameter Power Supply Voltage Reference Voltage, External Compensation Capacitor Output Load Ambient Temperature, Still Air
Min 3.0 1.0
Typ 3.3 1.25 0.1 37.5
Max 3.6 1.5
Unit V V F C
3
-40
+125
(c)2009 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
Electrical Characteristics
(TA = 25C, VDDA = VDDD =3.3V, VREF = 1.25V, RL = 37.5, unless otherwise noted)
Symbol
IDD PD
Parameter
Power Supply Current Total Power Dissipation(2) Input Voltage, HIGH (1) Input Voltage, LOW (1) Input Current, HIGH Input Capacitance Output Current (1)
(1)
Conditions
TA = 25C
(1)
Min
Typ
80
Max
85 95 300
Units
mA mA
TA = -40C to +125C (2) TA = -40C to +125C TA = -40C to +125C TA = -40C to +125C TA = -40C to +125C TA = -40C to +125C -1 -1 4 2.5
CDK3404 8-bit, 180MSPS, Triple Video DACs
mW V
Digital Inputs
VIH VIL IIH IIL CI 0.8 1 1 V A A pF 30 40 7 TA = -40C to +125C 1.135 1.25 1.365 mA k pF V
Input Current, LOW (1)
Analog Outputs
RO CO VREF Output Resistance Output Capacitance Reference Voltage Output (1)
Reference Output
Notes: 1. 100% tested at 25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
Switching Characteristics
(TA = 25C, VDDA = VDDD =3.3V, VREF = 1.25V, RL = 37.5, unless otherwise noted)
Symbol
Clock Input
Conversion Rate (1) tPWH tPWL Pulse-width HIGH (2) Pulse-width LOW
(2)
Parameter
Conditions
TA = -40C to +125C TA = -40C to +125C TA = -40C to +125C TA = 25C (1) TA = -40C to +125C TA = 25C (1) TA = -40C to +125C (2) TA = -40C to +125C TA = -40C to +125C TA = -40C to +125C
(2)
Min
Typ
Max
180
Units
MSPS ns ns ns ns
Rev 3A
2 2 1.5 2 0.6 0.6 1.6 0.6 0.4 2.5 0.3
Data Inputs
tS tH Setup Hold
ns ns ns ns ns ns ns
Data Outputs, with 50 doubly terminated load
tD tR tF tSET tSKEW
Notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
Clock to Output Delay Output Risetime Output Falltime Settling Time Output Skew
(c)2009 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
DC Performance
(TA = 25C, VDDA = VDDD =3.3V, VREF = 1.25V, RL = 37.5, unless otherwise noted)
Symbol Parameter
Resolution INL DNL Integral Linearity Error Differential Linearity Error Offset Error Gain Matching Error Absolute Gain Error TA = 25C
(1)
Conditions
Min
8 -0.5 -0.5 -0.5
(2)
Typ
Max
0.5 0.5 0.5 0.5 0.01 2.5 3.5
Units
bits LSB LSB LSB LSB %FS %FS %FS mA mA mA
CDK3404 8-bit, 180MSPS, Triple Video DACs
TA = -40C to +125C (2) TA = 25C (1) TA = -40C to +125C TA = -40C to +125C (2) TA = -40C to +125C (1) TA = -40C to +125C TA = 25C (1)
(1)
-0.5 -2.5 -3.5 18.0 18.0 18.7 18.7 18.7 -0.01 0
19.4 19.4
Full-Scale Output Current
TA = -40C to +125C (2) TA = -40C to +125C , With internal reference. Trim RSET to calibrate full-scale current. TA = -40C to +125C (2)
PSRR
Notes:
Power Supply Rejection Ratio
0.01
%/%
1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
AC Performance
(TA = 25C, VDDA = VDDD =3.3V, VREF = 1.25V, RL = 37.5, unless otherwise noted)
Symbol Parameter
Glitch Energy DAC-to-DAC Crosstalk Data Feedthrough Clock Feedthrough
Notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
Conditions
Min
Typ
20 30 50 60
Max
Units
pVsec dB dB dB
Analog Outputs
Rev 3A
(c)2009 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Table 1. Output Voltage vs. Input Code, SYNC and BLANK, VREF = 1.25V, RREF = 348, RL = 37.5
RGB7-0 (MSB...LSB) BLUE AND RED SYNC BLANK VOUT (V) SYNC GREEN BLANK VOUT (V)
1111 1111 1111 1111 1111 1110 1111 1101 * * 1000 0000 0111 1111 0111 1111 * * 0000 0010 0000 0001 0000 0000 0000 0000 XXXX XXXX XXXX XXXX
1 0 1 1 * * 1 1 0 * * 1 1 1 0 1 0
1 1 1 1 * * 1 1 1 * * 1 1 1 1 0 0
0.700 0.700 0.697 0.659 * * 0.351 0.349 0.349 * * 0.005 0.003 0.000 0.000 0.000 0.000
1 0 1 1 * * 1 1 0 * * 1 1 1 0 1 0
1 1 1 1 * * 1 1 1 * * 1 1 1 1 0 0
1.007 0.700 1.004 1.001 * * 0.658 0.656 0.349 * * 0.312 0.310 0.307 0.000 0.307 0.000
CDK3404 8-bit, 180MSPS, Triple Video DACs
tPWL
CLK
tPWH
1/fs
Rev 3A
ts
Pixel Data and Controls Data N
tH
Data N+1 Data N+2
3%/FS 90% tSET tF 10% tR
tD OUTPUT 50%
Figure 1. CDK3404 Timing Diagram
(c)2009 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Functional Description
Within the CDK3404 are three identical 8-bit D/A converters, each with a current source output. External loads are required to convert the current to voltage outputs. Data inputs RGB7-0 are overridden by the BLANK input. SYNC = H activates, sync current from IOS for sync-on-green video signals.
V DDA IOS SYNC G7-0 V DDA
BLANK gates the D/A inputs. If BLANK = HIGH, the D/A inputs control the output currents to be added to the output blanking level. If BLANK = Low, data inputs and the pedestal are disabled.
CDK3404 8-bit, 180MSPS, Triple Video DACs
Data: 660mV max.
Pedestal: 54mV Sync: 286mV
V DDA B7-0
Figure 3. Normal Output Levels Sync Pulse Input - SYNC Bringing SYNC LOW, disables a current source which superimposes a sync pulse on the IOG output. SYNC and pixel data are registered on the rising edge of CLK. SYNC does not override any other data and should be used only during the blanking interval. If sync pulses are not required, SYNC should be connected to GND. Blanking Input - BLANK When BLANK is LOW, pixel data inputs are ignored and the D/A converter outputs are driven to the blanking level. BLANK is registered on the rising edge of CLK.
V DDA R7-0
Figure 2. CDK3404 Current Source Structure
Digital Inputs
Incoming GBR data is regsitered on the rising edge of the clock input, CLK. Analog outputs follow the rising edge of CLK after a delay, tDO. Clock Input - CLK Pixel data is registered on the rising edge of CLK. CLK should be driven by a dedicated buffer to avoid reflection induced jitter, overshoot, and undershoot. Pixel Data Inputs - R7-0, B7-0, G7-0 RGB digital inputs are registered on the rising edge of CLK.
Rev 3A
D/A Outputs
Each D/A output is a current source from the VDDA supply. Expressed in current units, the GBR transformation from data to current is as follows: G = G7-0 & BLANK + SYNC * 112 B = B7-0 & BLANK R = R7-0 & BLANK Typical LSB current step is 73.2A. To obtain a voltage output, a resistor must be connected to ground. Output voltage depends upon this external resistor, the reference voltage, and the value of the gain-setting resistor connected between RREF and GND. To implement a doubly-terminated 75 transmission line, a shunt 75 resistor should be placed adjacent to the analog output pin. With a terminated 75 line connected to the analog output, the load on the CDK3404 current source is 37.5.
www.cadeka.com
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 3 and Table 1, on the previous page) of the D/A converters during CRT retrace intervals. BLANK forces the D/A outputs to the blanking level while SYNC = L turns off a current source, IOS, that is connected to the green D/A converter. SYNC = H adds a 112/256 fraction of full-scale current to the green output. SYNC = L extinguishes the sync current during the sync tip.
(c)2009 CADEKA Microcircuits LLC
7
Data Sheet
The CDK3404 may also be operated with a single 75 terminating resistor. To lower the output voltage swing to the desired range, the nominal value of the resistor on RREF should be doubled. R, G, and B Current Outputs - IOR, IOG, IOB Current source outputs can drive VESA VSIS, and RS343A/SMPTE-170M compatible levels into doubly-terminated 75 lines. Sync pulses can be added to the green output. When SYNC is HIGH, the current added to IOG is: IOS = 2.33 (VREF/ RREF) Current-Setting Resistor - RREF Full-scale output current of each D/A converter is determined by the value of the resistor connected between RREF and GND. Nominal value of RREF is found from: RREF = 5.31 (VREF/IFS) where IFS is the full-scale (white) output current (in amps) from the D/A converter (without sync). Sync is 0.439 * IFS. D/A full-scale (white) current may also be calculated from: IFS = VFS/RL Where VFS is the white voltage level and RL is the total resistive load () on each D/A converter. VFS is the blank to full-scale voltage.
and GND. Voltage across RSET is the reference voltage, VREF, which can be derived from either the 1.25 volt internal bandgap reference or an external voltage reference connected to VREF. To minimize noise, a 0.1F capacitor should be connected between VREF and ground. ISET is mirrored to each of the GBR output current sources. To minimize noise, a 0.1F capacitor should be connected between the COMP pin and the analog supply voltage VDDA. Voltage Reference Output/Input - VREF An internal voltage source of +1.25V is output on the VREF pin. An external +1.25V reference may be applied to override the internal reference. Decoupling VREF to GND with a 0.1F ceramic capacitor is required.
CDK3404 8-bit, 180MSPS, Triple Video DACs
Power and Ground
Required power is a single +3.3V supply. To minimize power supply induced noise, analog +3.3V should be connected to VDDD and VDDA pins with 0.1F and 0.01F decoupling capacitors placed adjacent to each VDD pin or pin pair. The high slew-rate of digital data makes capacitive coupling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video output signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise performance. All ground pins should be connected to a common solid ground plane for best performance.
Rev 3A
Voltage Reference
Full scale current is a multiple of the current ISET through an external resistor, RSET connected between the RREF pin
(c)2009 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
Applications Dicussion
Figure 5 (on the following page) illustrates a typical CDK3404 interface circuit. In this example, an optional 1.2V bandgap reference is connected to the VREF output, overriding the internal voltage reference source.
4. If the digital power supply has a dedicated power plane layer, it should not be placed under the CDK3404, the voltage reference, or the analog outputs. Capacitive coupling of digital power supply noise from this layer to the CDK3404 and its related analog circuitry can have an adverse effect on performance. 5. CLK should be handled carefully. Jitter and noise on this clock will degrade performance. Terminate the clock line carefully to eliminate overshoot and ringing.
CDK3404 8-bit, 180MSPS, Triple Video DACs
Grounding
It is important that the CDK3404 power supply is wellregulated and free of high-frequency noise. Careful power supply decoupling will ensure the highest quality video signals at the output of the circuit. The CDK3404 has separate analog and digital circuits. To keep digital system noise from the D/A converter, it is recommended that power supply voltages come from the system analog power source and all ground connections (GND) be made to the analog ground plane. Power supply pins should be individually decoupled at the pin.
Improved Transisiton Times
Output shunt capacitance dominates slowing of output transition times, whereas series inductance causes a small amount of ringing that affects overshoot and settling time. With a doubly terminated 75 load, transition times can be improved by matching the capacitive impedance output of the CDK3404. Output capacitance can be matched with a 220nH inductor in series with the 75 source termination.
IOG 32 W1 COAX R1 75
Printed Circuit Board Layout
Designing with high-performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor D/A conversion. Consider the following suggestions when doing the layout: 1. Keep the critical analog traces (VREF, IREF, COMP, IOS, IOR, IOG) as short as possible and as far as possible from all digital signals. The CDK3404 should be located near the board edge, close to the analog out-put connectors. 2. The power plane for the CDK3404 should be separate from that which supplies the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the CDK3404 is the same as that of the system's digital circuitry, power to the CDK3404 should be decoupled with 0.1F and 0.01F capacitors and isolated with a ferrite bead. 3. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads.
U1 CDK3404
IOB 29
W2 COAX R2 75
Rev 3A
IOR
33
W3 COAX R3 75 L1 220nH R4 75 L2 220nH R5 75 L3 220nH R6 75
Figure 4. Schematic, Transition Time Sharpening Circuit A 220nH inductor trims the performance of a 4ft cable, quite well. In Figures xx through xx, the glitch at 12.5ns, is due to a reflection from the source. Not shown, are smaller glitches at 25 and 37.5ns, corresponding to secondary and tertiary reflections. Inductor values should be selected to match the length and type of the cable.
(c)2009 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -5 0 5 10 15 20
0.8 0.7 0.6 0.5 0.4 0.3
GOUT (V)
ROUT (V)
CDK3404 8-bit, 180MSPS, Triple Video DACs
0.2 0.1 0
-0.1 -0.2 -5 0 5 10 15 20
Time (ns)
Time (ns)
Figure 5. Unmatched tR
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -5 0 5 10 15 20 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -5
Figure 7. Unmatched tF
GOUT (V)
GOUT (V)
0
5
10
15
20
Time (ns)
Time (ns)
Figure 6. Matched tR
+3.3V
Figure 8. Matched tF
Rev 3A
0.1F 0.01F
10F
0.1F
VDDD GND VDDA
RED PIXEL INPUT GREEN PIXEL INPUT BLUE PIXEL INPUT CLOCK SYNC BLANK
IOR IOG 75 75 75 COMP 0.1F V REF R REF VDDA
Red
Zo = 75
75 75 75
R7-0 G7-0 B7-0 CLK SYNC BLANK
Green w/Sync
Zo = 75
Blue
Zo = 75
CDK3404
Triple 8-bit D/A Converter
IOB
(not required without external reference)
3.3k
LM185-1.2 348
(Optional)
0.1F
Figure 9. Typical Interface Circuit Diagram Evaluation boards are available (CEB3400), contact CADEKA for more information.
Related Products
n n
CDK3400/3401 Triple 10-bit 180MSPS DACs CDK3404 Triple 8-bit 180MSPS DAC
www.cadeka.com
(c)2009 CADEKA Microcircuits LLC
10
Data Sheet
Mechanical Dimensions
LQFP-48 Package
CDK3404 8-bit, 180MSPS, Triple Video DACs
Rev 3A
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2009 by CADEKA Microcircuits LLC. All rights reserved.
A m p l i fy t h e H u m a n E x p e r i e n c e

▲Up To Search▲

Price & Availability of CDK3404

	To Download CDK3404 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .